Programm

Werfen Sie hier einen Blick auf das Programm zu den
ARROW Technologies Days
2017, die am 19. und 20. Juni 2017 stattfanden.

Während der Sessions-Slots wurden parallele Tracks angeboten:
  • FPGA Technology
  • Motion & Smart Power
  • High Speed Interfaces
  • Hands On/Workshop
    (Im Preis für das Altera-Hand-on-Training ist das Entwicklungsboard DE0-CV auf Basis eines FPGAs aus der Altera-Familie Cyclone V enthalten. Das Board besitzt einen Marktwert von ca. 150 Dollar. Weiter Details zum Board DE0-CV finden Sie hier.)

Einen Rückblick auf detaillierte Programm können Sie hier werfen.

Zwischen den verschiedenen Tracks bestand die Möglichkeit zu springen.

Einen Programmflyer zum Download finden Sie hier.

Montag, 19. Juni 2017

09:00 Uhr
Showcase
11:00 Uhr
Keynote
12:00 Uhr
Lunch/ Showcase

Parallele Sessions I

13:00 Uhr

Track 1 - Microsemi: High speed connectivity with PCIe Gen 3, high density switch for computing and graphics embedded connectivity. (englisch) mehr
Course that focuses in detail on the PFX family of PCIe Gen3 Fanout Switches, that consume 30% less power than competitive solutions. A solution that minimizes BOM cost, provides the highest reliability and flexibility and supports dynamic bi-furcation from 16-lanes down to 2-lanes per port. Target applications will be shown; datacenter, communications, defense, industrial servers, workstations, test equipment, video production and broadcasting equipment, cellular infrastructure, access networks, metro networks, and core networking.
Overview and capabilities of the Evaluation kits to support this innovative and competitive product will be given. Complementary Microsemi products that fit around the fan out switch will also be discussed, enabling you to design a multichip solution from one supplier.
Referent: Richard Cannon | Microsemi
Track 2 - TE Connectivity: High Speed Data Communication (englisch) mehr
TE Connectivity (TE) has always been at the forefront of innovation, and with a broad portfolio of new and standard products, TE continues to lead the development of data and industrial communication solutions for the quickly changing market needs. Next to that, TE understands the industry's need for reliable connectivity that delivers greater simplicity, efficiency and uptime – especially when it comes to smart factories and ever-increasing data demands. This is why TE’s communications and networking solutions are geared to the most demanding environments and requirements of manufacturers worldwide. During this training session TE will present high speed connectivity products focusing on FPGA and chipset solutions. 
Referent: Frank Hayes | TE Connectivity
Referent: Frank Kreutz | TE Connectivity
Track 3 - Intel PSG (Altera): Enabling the next generation of low-cost applications with Intel’s Cyclone 10 FPGAs (englisch) mehr
Learn about Intel’s latest generation of low-cost FPGAs, with an overview and a discussion on their features and benefits. The session will finish with a focus on end application areas, and the value that Cyclone 10 and MAX10 can bring. Solutions for the automotive and industrial markets will also be demonstrated.
Referent: Mark Frost | Altera
Track 4 - Amphenol: Board Level Interfaces - Chasing The Need For Speed (englisch)
Referent: Thierry Goossens | Amphenol
Track 5 - HandsOn: Introduction to Intel FPGA (englisch) mehr
This training program provides theoretical and practical know-how to design Intel FPGA using Quartus Prime software tools. The course intention is to train electronics engineers, FPGA to start working with Intel FPGAs. The course combines 50% theory with 50% practical work. The course begins with an overview of the current Intel programmable logic devices and their capabilities. The course continuous with an overview of Quartus Prime features, projects types and management, design methodology, and using IP cores from the IP catalog, as well as the assignment editor and pin planner tool. Qsys system integration tool, state machine editor, memory editor, Altera SD for OpenCL, and DSP Builder are also introduced in high level. The course continuous with Quartus Prime compilation flow, incremental compilation concept, viewing compilation reports, RTL and technology views, and how to use the chip planner tool.
Referent: Oren Hollander | HandsOn Training
14:30 Uhr
Networking Break/ Showcases

Parallele Sessions II

15:00 Uhr

Track 1 - Microsemi: Differentiating Microsemi’s newest PolarFire Flash based, low power FPGA family versus, SRAM FPGA’s mehr
Showing how PolarFire has been designed to be a fraction of the power of any SRAM FPGA. Targeting applications that are challenging for power hungry SRAM FPGA's, combining that with unique reliability, high speed and providing the high levels of security, needed in today's "cyber security" world . A detailed outline of the many IP Cores that is available to support the introduction of this new FPGA family.  Development kits and evaluation boards for this unique family of FPGA's will be shown, along with an introduction to the Arrow Everest board that is being designed to support and facilitate the easy design in of PolarFire in your target application.
Application examples will be given on utilizing this new FPAG family for a wide range of applications such as wireline access networks, cellular infrastructure, defense, commercial aviation as well as industrial automation and IoT markets.  
Referent: Olaf Juergens | Microsemi
Track 2 - STMicroelectronics: Smart Factory - Driving the Industry 4.0 (englisch) mehr
The course provides an overview of STMicroelectronics´ solutions for Factory Automation and Industry 4.0. Special focus will be put on our latest Intelligent Power Switches and Current Limited Terminations including the solutions for IO-Link (industry-leading standard for smart networking of sensors & actuators).
You will be shown how the new innovative features of these products match with the challenging requirements of Industry 4.0.
Referent: Vojtech Elias | STMicroelectronics
Track 4 - Microchip: Board interfaces: Ethernet PHYs and Industrial Ethernet solutions, including USB 3.x solutions (englisch)
Referent: Matthias Goeing | Microchip
Track 5 - HandsOn: Introduction to Intel FPGA (englisch) mehr
This training program provides theoretical and practical know-how to design Intel FPGA using Quartus Prime software tools. The course intention is to train electronics engineers, FPGA to start working with Intel FPGAs. The course combines 50% theory with 50% practical work. The course begins with an overview of the current Intel programmable logic devices and their capabilities. The course continuous with an overview of Quartus Prime features, projects types and management, design methodology, and using IP cores from the IP catalog, as well as the assignment editor and pin planner tool. Qsys system integration tool, state machine editor, memory editor, Altera SD for OpenCL, and DSP Builder are also introduced in high level. The course continuous with Quartus Prime compilation flow, incremental compilation concept, viewing compilation reports, RTL and technology views, and how to use the chip planner tool.
Referent: Oren Hollander | HandsOn Training
16:30 Uhr
Networking Break/ Showcases
19:00 Uhr
Dinner
22:00 Uhr
Ende des 1. Veranstaltungstages

Dienstag, 20. Juni 2017

Parallele Sessions III

09:00 Uhr

Track 1 -
FTDI: FTDI USB bridges to interface with system logic (englisch)

Pulse: High Speed communication. The Copper option. Ethernet and USB in your network! (englisch) mehr
FTDI: FTDI USB bridges to interface with system logic (english)

FTDI is renowned for their USB bridges to UART and other interfaces. A short presentation on the various options available will be delivered.
We will look at the different interface types and the pros and cons of such interfaces
The advances in USB speed options will be discussed with a view to the applications where they are most appropriate and the trade-offs with speed vs power consumption.
Looking specifically at programmable logic we will explore why a USB bridge between the development PC and the target hardware makes for the best interface through its ease of use, power delivery and low pin count.



Pulse: High Speed communication. The Copper option. Ethernet and USB in your network! (english)
Referent: 1) Gordon Lunn | FTDI
Referent: 2) Grahame Lockey | Pulse
Track 2 - Microchip: MEMs Oscillators and Clocking/Timing: Usage of the right oscillator and building efficient clocking trees (englisch)
Referent: Matthias Goeing | Microchip
Track 3 - HandsON: Timing Closure for FPGAs (englisch) mehr
This course provides theoretical and practical know-how to analyze and fix timing failures for variety use cases in Intel FPGAs
The course goes into great depth and touches upon every aspect of timing failures due to setup and hold negative slack, I/O input/output delays, reset issues, high fanout, global clock networks, over constrained design, as well as timing exceptions. The course begins with SDC and timing reports review to highlight which constraints and reports should be written and generated, and when to use each. Then timing closure recommended methodology is discussed with various Quartus Prime tools and advanced settings. The course continues with an in depth solutions for various timing failures use cases such as too many logic levels, high fanout, confliction SDC assignments, conflicting location assignments, tight timing requirements, clock crossing, and clock skew.
Referent: Oren Hollander | HandsOn Training
Track 4 -
Arrow SOM: Make or Buy - System on Modules

Dreamchip: Embedded Linux with 10G Ethernet and hardware accelerated 4K real-time streaming engine mehr
Make or Buy - System on Modules:

Make or Buy, das ist die Frage, welche sich viele Unternehmen heut zu Tage stellen. Das Ziel neueste Produkte immer schneller auf den Markt zu bringen und das bei immer komplizierter werden Prozessoren, sind große Herausforderungen. Dazu kommt noch, dass der Softwareumfang überproportional zunimmt. Durch die Vielzahl von System-on-Modules und deren individuellen Unterschieden vor allem auch im Bereich Software/Betriebssysteme, ist eine kompetente Beratung enorm wichtig. Das Zusammenspiel aus Stückzahl, Preis, Features und eigenen Ressourcen, führt letztendlich zur Beantwortung der Kernfrage "Make or Buy", welche im Vortrag erläutert wird.



Embedded Linux with 10G Ethernet and hardware accelerated 4K real-time  streaming engine:

This presentation covers a high performance video streaming application in combination with an embedded Linux system on an Intel ARRIA10 FPGA. Whereas the 4k real-time streaming part including previous processing of the data is implemented in the FPGA part of the Intel ARRIA10, the high level control including all the Internet Protocol stack features like ARP, DHCP, ICMP, IGMP etc. are handled by the Linux network stack. All network packets are transmitted via one 10G Ethernet physical interface. In addition, the principles of SMPTE 2059/IEEE1588v2 genlock over IP networks will be explained.


Referent: 1) Dieter Kiermeier | Arrow
Referent: 2) Heiko Henkel | Dreamchip Technologies
10:30 Uhr
Networking Break/ Showcases

Parallele Sessions IV

11:00 Uhr

Track 1 - Intel PSG (Altera): FPGA brings the Acceleration, Connectivity, Security and Safety in one Device for IIOT mehr
IoT adoption in 3 steps
  • First  extract data from fixed function systems for insights and Early OT to IT type of conversions
  • Second Machines and sensors built from ground up to be intelligent, and interconnected
  • Third Software-defined world allows for application ecosystem, New merged stack is optimized for machine apps allowing for use cases not possible today, Flexible and learning based platform allows innovation on long-life deployed assets
FPGA support all 3 step and more!
Referent: Karl Wachswender | Altera
Track 2 - STMicroelectronics: Motor Control - Smart Motion with STSPINTM (englisch) mehr
Attendees of this course will get the full overview of the monolithic solutions for motor control applications in the range of 1.8V up to 85V . The key technical features and advantages of the STSPINpower, STSPINdigital and the brand new STSPINbattery product lines will be explained in particular. They are extending our broad portfolio of robust, smart and flexible devices with and even higher integration in very compact power packages.    
Referent: Dr. Basam Elia | STMicroelectronics
Track 3 - HandsOn: Timing Closure for FPGAs (englisch) mehr
This course provides theoretical and practical know-how to analyze and fix timing failures for variety use cases in Intel FPGAs
The course goes into great depth and touches upon every aspect of timing failures due to setup and hold negative slack, I/O input/output delays, reset issues, high fanout, global clock networks, over constrained design, as well as timing exceptions. The course begins with SDC and timing reports review to highlight which constraints and reports should be written and generated, and when to use each. Then timing closure recommended methodology is discussed with various Quartus Prime tools and advanced settings. The course continues with an in depth solutions for various timing failures use cases such as too many logic levels, high fanout, confliction SDC assignments, conflicting location assignments, tight timing requirements, clock crossing, and clock skew.
Referent: Oren Hollander | HandsOn Training
Track 4 -
Dreamchip: Image Signal Processing based on Intel MAX10 for camera applications

Kemet: Output capacitors technologies for DC/DC converter to support FPGA´s mehr
Image Signal Processing based on Intel MAX10 for camera applications:

Based on two demonstrators of image sensors you will see how to implement a real camera system into an MAX10 FPGA. With the image signal processing software, there will be done various corrections and manipulations of the image data, to get the best output performance and picture of the sensor, depending on the application.



Output capacitors technologies for DC/DC converter to support FPGA´s:

With changing requirements of DC/DC converter with lower voltages and high output currents traditional technologies are challenged and will not be the best choice anymore. Specifically when output currents can change quickly there are capacitor technologies which can support higher currents and load changes much better. All of those technologies are linked to a polymer cathode material which enables conservative technologies to compete with latest Semiconductor requirements such as FPGA´s as well as processors and in general single board computers for decoupling.


Referent: 1) Heiko Henkel | Dreamchip Technologies
Referent: 2) Michael Freitag | Arrow - KEMET Electronics
12:30 Uhr
Lunch/ Showcases

Parallele Sessions V

13:30 Uhr

Track 1 - Intel PSG (Altera): Embedded Vision mehr
Big Data => IP Cameras will produce  1.6 Exabytes of data per day by 2020.
Better Hardware => Computing performance increases by more than an order of magnitude each decade.  FPGAs significantly impact MIPS/W of smart vision systems.
Smarter Algorithms => Advances in neural networks are leading to better accuracy.  High performance computing and acceleration of analytics enable smart vision.
Referent: Karl Wachswender | Altera
Track 2 - STMicroelectronics: Motor Control - 50W-3kW Industrial Motor Control with Smart and Compact Inverter solutions for BLDC Motors. (englisch) mehr
In this course we are addressing 3-phase BLDC motor control solutions in the range of 50W up to 3kW. We will show you our highly integrated and robust SLLIMM™  family of MOSFET and IGBT based Intelligent Power Modules as well as ST´s latest extension of smart gate drivers and power transistors. The differences and individual benefits of using MOSFETS or IGBTs in inverters will be covered, underlined with real case benchmarks and measurements from ST´s Power Application lab.
Referent: Ales Loidl | STMicroelectronics
Track 3 - HandsOn: Timing Closure for FPGAs (englisch) mehr
This course provides theoretical and practical know-how to analyze and fix timing failures for variety use cases in Intel FPGAs
The course goes into great depth and touches upon every aspect of timing failures due to setup and hold negative slack, I/O input/output delays, reset issues, high fanout, global clock networks, over constrained design, as well as timing exceptions. The course begins with SDC and timing reports review to highlight which constraints and reports should be written and generated, and when to use each. Then timing closure recommended methodology is discussed with various Quartus Prime tools and advanced settings. The course continues with an in depth solutions for various timing failures use cases such as too many logic levels, high fanout, confliction SDC assignments, conflicting location assignments, tight timing requirements, clock crossing, and clock skew.
Referent: Oren Hollander | HandsOn Training
Track 4 -
Exor: Iot Controller FPGA based (englisch)

Reflex: Arria 10 SoC Most Integrated System-On-Module (englisch) mehr
Iot Controller FPGA based:

New generations of controllers are required in industrial automation.
We can talk about IoT Controller, as a generation of controllers capable of working as a PLC, and as a gateway to interface to the Cloud.
The next-generation CPUs are not able to meet the requirements of these new systems.
Exor proposes an innovative solution based on Intel Cyclone FPGA in order to realize new IoT in a versatile manner and fully programmable controller and to meet the requirements of interfacing with emerging systems such as fieldbus side TSN.



Arria 10 SoC Most Integrated System-On-Module:

ReFLEX CES will introduce the most integrated and full of features Arria 10 SoC System-On-Module and all its eco-system of starter board and PCIe board to prototype and go easy and fast to production.
A System-On-Module makes customer like much easier to get and FPGA SoC solution and let him focus on its real added value at system and application levels.

Referent: 1) Claudio Ambra | Exor Embedded
Referent: 2) Vincent Martinez | Reflex Ces
15:00 Uhr
Networking Break/ Showcases

Parallele Sessions VI

15:15 Uhr

Track 1 -
Arrow: Nios II Soft-CPU im Arrow MAX1000 Board

Enpirion: Enpirion Power Solutions mehr
Arrow: Nios II Soft-CPU im Arrow MAX1000 Board:

Das Arrow MAX1000 Board ist ein kleines Low-Cost Board mit dem MAX10 FPGA von Intel, das sowohl für den Einsatz als Eval-Plattform, als auch für Produktivsysteme geeignet ist.
Nach einer kurzen Vorstellung des Boards soll in einem praktischen Teil die grundlegende Implementierung einer Nios II Soft-CPU inklusive Peripherie gezeigt werden.


Enpirion Power Solutions:

Intel® Enpirion® Power Solutions provide high-efficiency power management for FPGAs, SoCs and Microprocessors. These robust, easy-to-use products meet your most stringent power requirements—all in a small footprint. Enpirion devices are highly integrated DCDC modules with an integrated inductor, resulting in a minimum need of external components. The modules have superior efficiency and best in class load transient response, to meet the high accuracy requirements of FPGA core voltages. The latest family member EM2130 supports up to 30A output current over full temperature range and has an implemented PMBus interface for FPGA core voltage regulation. 
Referent: 1) Michael Fuhrmann | Arrow
Referent: 2) Christian Höfling | Enpirion
Track 2 -
Arrow: Echtzeit Ethernet mit STM32

Arrow: Echtzeit Betriebssysteme mit STM32
Referent: 1) + 2) Klaus Kohl-Schöpe | Arrow
Track 3 - HandsOn: Timing Closure for FPGAs (english) mehr
This course provides theoretical and practical know-how to analyze and fix timing failures for variety use cases in Intel FPGAs
The course goes into great depth and touches upon every aspect of timing failures due to setup and hold negative slack, I/O input/output delays, reset issues, high fanout, global clock networks, over constrained design, as well as timing exceptions. The course begins with SDC and timing reports review to highlight which constraints and reports should be written and generated, and when to use each. Then timing closure recommended methodology is discussed with various Quartus Prime tools and advanced settings. The course continues with an in depth solutions for various timing failures use cases such as too many logic levels, high fanout, confliction SDC assignments, conflicting location assignments, tight timing requirements, clock crossing, and clock skew.
Referent: Oren Hollander | HandsOn Training
16:45 Uhr
Ende der Veranstaltung

Showcase - Ausstellung - Messe

Während beider Tage fand parallel zum Vortragsprogramm ein Showcase statt, in welchem sich die Hersteller der Tracks in einer Ausstellung präsentierten. Hier hatten die Teilnehmer die Gelegenheit mit den Spezialisten direkt im Detail zu sprechen und diverse Applikationen anhand von Demos zu begutachten. Auch Arrow selbst zeigte sein umfassendes Portfolio an Lösungen und Demos für verschiedenste Märkte. Als technische/kommerzielle Ansprechpartner standen die verschiedensten Arrow-Spezialisten für die Teilnehmer bereit und freuten sich, ihnen mit Rat und Tat bei ihren täglichen Herausforderungen zur Seite zu stehen.

Ebenfalls gab es weitere diverse kostenlose Developmentskits von den Herstellern auf dem Showcase, je nach Applikation und Interesse.

Hauptsponsoren 2017

Sponsoren 2017

Partner 2017